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Home → No Data → No Data → No Data Overview LAYED is a powerful all-angles graphics editor especially developed for the layout of complex integrated circuits, including analog, digital, and mixed-signal designs. Impressive features of the layout editor include a rich command set, hierarchically structured databases, very fast redraw speed and screen refresh. Data can be imported or exported in standard exchange formats (GDS2, CIF, GERBER, DXF). This IC editor also supports parametric groups (PGroups) and a schematic-driven layout option to facilitate accurate and productive layout generation. Basic Features• Data items include polygons, rectangles, lines, paths, circles, arcs, groups, or arrays of groups.
• 256 layers supported
• 256 data types fully supported
• All-angle, 45-degree, and Manhattan options
• Data may be entered hierarchically (up to 30 levels)
• Supports multiple design windows (customizable window count)
• Full-function edit-in-place
• Data may be accessed from up to 19 reference libraries
• Data may be imported / exported in various standard formats (GDS2, CIF, GERBER, DXF)
• Optional supervision of imported data to ensure data integrity (vertex count; edge length)
• Flexible command entry – keyboard, hot-key, menu bar, tool bar, layer bar, mouse, command file
• Command files include command procedures, allow access to databases, provide variable definition and subroutines
• Case-sensitive structure names
• Comprehensive data selection criteria for objects and vertices
• Advanced edit features including cut and merge, group creation from selected objects, etc.
• Advanced analysis features (including connectivity and on-line DRC)
• Accelerated display for large designs
• Supports ports and item properties
• Polygon closure preview Advanced Features • Easily configured for immediate design entry using initialization files
• Network licensing and shared database management
• Connectivity display (node highlighting by connection rather than text)
• Command file procedures supported
• Provides schematic driven layout with SPE (option)
• On-line DRC (option)
• Seamless interface to LAYVER verification databases to interrogate violations (option)
• Interface to launch LAYVER which picks up verification window, group name, and reference libraries
• Parametric groups (PGroups) facilitate accurate device generation (option) 
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