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SPE

Overview

SPE (Schematic Probe Environment) is a flexible and powerful full-function multi-level schematic capture environment developed particularly to enable IC circuit design engineers to enter schematics accurately, clearly and quickly. In addition it provides the ability to cross-probe between schematic and layout views using the network extracted.

SPE includes many powerful features including the availability of an unlimited hierarchy which can be navigated from the design entry window with a single command. It offers a rich selection of digital and analog net-list formats and is closely linked to simulation environments allowing such advanced features as back annotation and voltage probing from simulation results.

Coupled with LAYED, SPE provides a schematic or net-list driven layout mode in which the layout implementation is monitored using the schematic or net-list.

Highlights

• Enables rapid entry of complex schematics
• Includes comprehensive editing features
• Provides easy navigation of design hierarchy
• Allows calculation and display of parameters
• Generates net-lists in various digital and analog formats
• Closely coupled with simulation tools
• Enables schematic-driven layout
• Allows cross-probing with layout

Feature Details

• Graphical data may be created and edited in an hierarchical set of schematic drawings
• Data is stored in ASCII format allowing conversion to standard or non-standard formats
• Edit flexibility includes copying between windows and sub-window drag
• Data elements include symbols, attributes, texts, wires, buses, bus taps, and pins (for wires and buses)
• Unlimited bus widths
• Deep “undo” stack (currently set at 64)
• No limit on design size or complexity
• Unlimited number of sheets in multiple sheet drawings
• Unlimited depth of design hierarchy
• Navigation of the design hierarchy is unrestricted and traversed from the design entry window
• Symbols for both primitive and sub-circuits can be auto-generated or customized
• Auto-generated symbols have no port count limit
• Symbols are characterized using user-defined attributes which may be calculated from other attributes
• Schematics and symbols may be organized in an unlimited number of reference directories
• Flexibility is provided for the naming format of nets and buses
• Standard net-list output formats are provided (device and gate level – including HSpice, PSpice, Verilog, and VHDL).
• Hierarchical integrity checks may be carried out (ERC)
• Cross-probing between SPE and LAYED may use the same system or different systems (“socket” connection)
• Schematic-driven layout (SDLE) possible when used with LAYED (option)
• Close coupling with simulation tools (SMASH ™ and SIMetrix™)