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Verification Decks

LAYTOOLS verification run-decks to check layout databases against foundry rules (drc) and against circuit net-lists (lvs) are available for a range of technology nodes and foundries. Run-decks to extract circuit devices and parasitic devices (lpe) are also offered. The run-decks have been written and tested and have been written by professionals who understand the technology and the sophistication of the LAYVER command structure. They offer, therefore, optimum checking times while ensuring complete check coverage and violation reporting. Run-time switches to disable certain features (antenna checks, coverage checks, latch-up checks, etc.) are included in drc decks. Parasitic extraction decks present area, fringe, and coupling capacitance elements while options allow disabling of contact and via resistance extraction and metal track resistance extraction.

Foundry-specific data is protected by providing it as an encrypted file which is automatically decrypted by LAYVER.